FPGA Implementation of 16-bit Multipliers based upon Vedic Mathematic Approach

FPGA Implementation of 16-bit Multipliers based upon Vedic Mathematic Approach

This paper proposes design and implementation of a 16-bit multiplier based upon Vedic mathematicapproach, where the design has been targeted to the Xilinx Field Programmable Gate Arrays (FPGAs) board, deviceXC5VLX30. The approach is different from a number of approaches that have been used to realize multipliers.  Ithas been reported that previous algorithms such as Booth, Modified Booth, and Carry  Save Multipliers only suitablefor improving  speed or decreasing area utilization; therefore, those algorithms are not appropriate for designingmultipliers that are used for digital signal processing (DSP) applications. Moreover, they are not flexible to beimplemented on FPGAs or on a single chip using application specific integration circuits (ASICs). Vedic approach,on the other hand, can be used to design multipliers with optimum speed and less area utilization. In addition, it isreliable to be implemented on FPGAs or on a single chip.  Behavioral and post-route simulation results prove that theproposed multiplier shows better performance in terms of speed compared to the other reported multipliers whenbeing  implemented on the FPGA. In terms of area utilization, better results are also obtained.

., Zulhelmi

Jurnal Rekayasa Elektrika; Vol 10, No 4 (2013); 166-171

2252-620X

1412-4785

Universitas Syiah Kuala

2014-03-20

http://jurnal.unsyiah.ac.id/JRE/article/view/1105/1024

application/pdf

eng

info:eu-repo/semantics/article

info:eu-repo/semantics/publishedVersion

Peer-reviewed Article

http://jurnal.unsyiah.ac.id/JRE/article/view/1105

10.17529/jre.v10i4.1105