Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

., Zulfikar

Jurnal Rekayasa Elektrika; Vol 10, No 2 (2012)

2252-620X

1412-4785

Universitas Syiah Kuala

2015-05-05

Copyright (c) 2015 Jurnal Rekayasa Elektrika

http://jurnal.unsyiah.ac.id/JRE/article/view/7/7

application/pdf

eng

info:eu-repo/semantics/article

info:eu-repo/semantics/publishedVersion

Peer-reviewed Article

http://jurnal.unsyiah.ac.id/JRE/article/view/7

10.17529/jre.v10i2.7